1. Field of the Invention
The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method thereof.
2. Description of the Related Art
Recently, with the purpose of improving integration, the shape having a practically vertical side surface is expected for a shape of a ferroelectric capacitor for example of the 0.18 μm generation. For this purpose, for example in a simultaneous etching at a high temperature using a hard mask, such a technique is beginning to be employed as etching simultaneously an upper electrode film, a ferroelectric film, and a lower electrode film. As a structure of the hard mask here, a lamination structure using a TEOS film and a TiN film is employed.
However, when employing the high-temperature simultaneous etching in the current process, those scattered substances, which are generated in the course of etching the ferroelectric film, may be deposited on a sidewall of the capacitor after changing their properties. Due to such deposits as exist on the sidewall, a leakage current may sometimes be caused between the upper electrode and the lower electrode. Therefore, it is conventionally designed to remove these deposits in the etching process of the lower electrode.
Meanwhile, the sidewall deposits have an effect of preventing the ferroelectric film from damages. Hence, when the sidewall deposits of the ferroelectric capacitor are completely removed in the manufacturing process of the conventional ferroelectric memory, the ferroelectric film locally suffers substantial heavy damages, making it impossible to obtain desired properties. Accordingly, in the conventional ferroelectric memory, it is impossible to prevent leakage current adequately. A prior art is disclosed for example in Japanese Patent Application Laid-Open No. 2003-092391.